| OID | 1.3.6.1.4.1.1570.1.6.4.1.6 |
| Module | Cisco90Series-MIB (CISCO) |
| Nom | frxAlertMask |
| Acces | readwrite |
| Status | mandatory |
| Description | 8-bit Alert Mask register. One bit for each threshold in both directions. When set to 1, the corresponding threshold crossing is ignored. When set to 0, the corresponding threshold crossing is indicated in frxThCond and may cause a trap to be sent depending on the state of frxUPerfTrapEnable. 1 Current Day Severely Errored Seconds Receive 2 Current Day Severely Errored Seconds Transmit 4 Current Day Errored Seconds Receive 8 Current Day Errored Seconds Receive 16 Current Hour Severely Errored Seconds Receive 32 Current Hour Severely Errored Seconds Transmit 64 Current Hour Errored Seconds Receive 128 Current Hour Errored Seconds Transmit Transmit is data from the customer towards the network. Receive is data from the network towards the Customer. This register is defined by Bellcore TR-TSY-000829. Indexed by Bank.ChannelUnit.Port.Address |
| Syntaxe | Integer32 (0...255) |